The embodiments presented herein relate to integrated circuits and, more particularly, to sequencing arithmetic operations in an integrated circuit.
Considering a programmable logic device (PLD) as one example of an integrated circuit, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include configurable specialized blocks in addition to blocks of generic programmable logic. Such specialized blocks may include circuitry that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation.
A specialized block may also contain one or more specialized structures. Examples of structures that are commonly implemented in such specialized blocks include multipliers, arithmetic logic units (ALUs), memory elements such as random-access memory (RAM) blocks, read-only memory (ROM) blocks, content-addressable memory (CAM) blocks and register files, AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of configurable specialized processing block that has been provided on programmable logic devices (PLDs) is a specialized processing block (SPB) that is often used in signal processing applications, which include the manipulation of data signals, audio signals, or video signals (as an example). Configurable specialized processing blocks may sometimes be referred to as multiply-accumulate (MAC) blocks, when they include structures to perform multiplication operations, summing operations, and/or accumulations of multiplication operations.